The present invention relates to a flat-cell ROM and decoder.
A flat-cell read-only memory (ROM) is formed on a substrate by implanting columns of buried N+ and depositing rows of polysilicon. Transistor channel regions are created between the buried N+ columns and under the polysilicon rows and are arranged in columns and rows corresponding to the buried N+ columns and polysilicon rows. The transistors each have a source, drain and gate, where the source and drain are represented by adjacent buried N+ columns and the gate is represented by the polysilicon row. Each transistor represents a ROM storage location.
The ROM storage value of each location depends on the amount of ion implantation (doping) that the channel receives. To program the ROM, all channel locations receive a blanket doping to develop transistors having a voltage threshold (Vt1) of approximately 0.7 V. Then, desired locations are programmed off by an additional ion implant, or target-doping, to develop transistors having a voltage threshold (Vt2) of approximately 6 V. As a result, the blanket-doped locations have a first value associated therewith and the target-doped locations have a second value associated therewith. Often these values are considered as binary values of "0" and "1."
If the channel is blanket-doped, it is considered a valid transistor and current flow from the source to drain begins once the threshold Vt1 is met at the gate. The arrangement where a column of storage locations share a common buried N+ source line and a common N+ drain line results in what is commonly referred to as a NOR array. That is, the addressed storage value is determined using what is known in the art as a Not-OR (NOR) table.
In a common NOR array, the buried N+ columns are considered bitlines and the polysilicon rows are considered wordlines. An address identified memory location is determined by decoding the bitlines and wordlines to activate the source, drain and gate of the memory location. For example, at a normal operating voltage where Vcc is 5 V, if the channel is blanket-doped, it conducts at a threshold of 0.7 V and a "0" is associated with the location, and if the channel is target-doped, it does not conduct and a "1" is associated with the location.
In practice, a flat-cell ROM is beneficial for high density memory storage. However, since the flat-cell concept requires columns of slow-conductivity buried N+, design limits are placed on the size of a flat-cell array. These design limits are primarily a matter of ROM access time; that is, a large array is dense but slow. To accommodate this design limit, banks of flat-cell arrays are connected to one another via metal bitlines, where a typical bank has 16 or 32 rows.
Another design difficulty involves selecting the memory locations. Several techniques have been introduced to overcome this hurdle. One technique involves pairing the columns and providing a selecting circuit to select one of the columns for output, however, this technique requires dedicated power lines and tight design tolerances due to close contact pitch. Another technique uses a zig-zag metal bitline layout but still requires tight design tolerances.
What is needed is a flat-cell ROM that has the benefits of high density and an efficient decoding and selection scheme, can selectively couple power and sense amplification to any column, and has a metal bitline pitch that permits easy manufacture and relaxed design tolerances.